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STLVD111
PROGRAMMABLE LOW VOLTAGE 1:10 DIFFERENTIAL LVDS CLOCK DRIVER
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100ps PART-TO PART SKEW 50ps BANK SKEW DIFFERENTIAL DESIGN MEETS LVDS SPEC. FOR DRIVER OUTPUTS AND RECEIVER INPUTS REFERENCE VOLTAGE AVAILABLE OUTPUT VBB LOW VOLTAGE VCC RANGE OF 2.375V TO 2.625V HIGH SIGNALLING RATE CAPABILITY (EXCEEDS 622MHz) SUPPORT OPEN, SHORT AND TERMINATED INPUT FAIL-SAFE (LOW OUTPUT STATE) PROGRAMMABLE DRIVERS POWER OFF CONTROL
TQFP32
DESCRIPTION The STLVD111 is a low skew programmable 1 to 10 differential LVDS driver, designed for clock distribution. The select signal is fanned out to 10 identical differential outputs. The STLVD111 is provided with a 11 bit shift register with a serial in and a Control Register. The purpose is to enable or power off each output clock channel and to select the clock input. The STLVD111 is specifically designed, modelled and ORDERING CODES
Type STLVD111BF STLVD111BFR Temperature Range -40 to 85 C -40 to 85 C Package
produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device. The net result is a dependable guaranteed low skew device. The STLVD111 can be used for high performance clock distribution in 2.5V systems with LVDS levels. Designers can take advantage of the device's performance to distribute low skew clocks across the backplane or the board.
Comments 250 parts per Tray 2400 parts per reel
TQFP32 (Tray) TQFP32 (Tape & Reel)
December 2002
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STLVD111
PIN CONFIGURATION
PIN DESCRIPTION
PlN N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2/12 SYMBOL CK SI CLK0 CLK0 VBB CLK1 CLK1 EN GND Q9 Q9 Q8 Q8 Q7 Q7 VCC Q6 Q6 Q5 Q5 Q4 Q4 Q3 Q3 GND Q2 Q2 Q1 Q1 Q0 Q0 VCC NAME AND FUNCTION Control Register Clock Control Register Serial IN/CLK_SEL Differential Input Differential Input Output Reference Voltage Differential Input Differential Input Device Enable/Program Ground Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Supply Voltage Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Ground Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Differential Outputs Supply Voltage
STLVD111
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IOSD ESD Supply Voltage Input Voltage Output Voltage Driver Short Circuit Current Electrostatic Discharge (HBM 1.5K, 100pF) Parameter Value -0.3 to 2.8 -0.2 to (VCC+0.2) -0.2 to (VCC+0.2) Continuous >2 KV Unit V V V
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
THERMAL DATA
Symbol RTj-c Parameter Thermal Resistance Junction-Case Value 13 Unit C/W
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIC TA TJ Supply Voltage Receiver Common Mode Input Voltage Operating Free-Air Temperature Range Operating Junction Temperature Parameter Min 2.375 0.5(VID) -40 -40 TYP Max 2.625 2-0.5(VID) 85 105 Unit V V C C
DRIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 C, VCC = 2.5V 5%, unless otherwise specified (Note 1, 2)
Value Symbol VOD VOD VOS VOS IOS Parameter Output Differential Voltage (Fig. 2) VOD Magnitude Change Offset Voltage VOS Magnitude Change Output Short Circuit Current VO = 0V VOD = 0V 15 7 RL = 100 Test Conditions Min. 400 Typ. 500 Max. 600 30 -40 TA 85C 1.05 1.15 1.25 30 30 15 mV mV V V mA Unit
NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. NOTE 2: All typical values are given for VCC = 2.5V and TA = 25C unless otherwise stated.
RECEIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 C, VCC = 2.5V 5%, unless otherwise specified (Note 1, 2)
Value Symbol VIDH VIDL IIN Parameter Input Threshold High Input Threshold Low Input Current VI = 0V VI = 0VCC -100 42 2 100 10 Test Conditions Min. Typ. Max. 100 mV mV A Unit
NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. NOTE 2: All typical values are given for VCC = 2.5V and TA = 25C unless otherwise stated.
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STLVD111
DRIVER ELECTRICAL CHARACTERISTICS (TA = -40 to 85 C, VCC = 2.5V 5%, unless otherwise specified (Note 1, 2)
Value Symbol VBB ICCD CIN COUT VIH VIL II Parameter Output Reference Voltage Power Supply Current Input Capacitance Output Capacitance Logic Input High Threshold Logic Input Low Threshold Logic Input Current VCC = 2.5 V VCC = 2.5 V VCC = 2.5 V, VIN = VCC or GND 2 0.8 10 Test Conditions Min. VCC = 2.5 V All driver enabled and loaded VI = 0V to VCC 1.15 Typ. 1.25 125 5 5 Max. 1.35 160 V mA pF pF V V A Unit
NOTE 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. NOTE 2: All typical values are given for VCC = 2.5V and TA = 25C unless otherwise stated.
LVDS TIMING CHARACTERISTICS (TA = -40 to 85 C, VCC = 2.5V 5%, unless otherwise specified (Note 4)
Value Symbol Parameter Test Conditions Min. tTLH, tTHL Transition Time tPHL, tPLH Propagation Delay Time fMAX tSKEW Maximum Input Frequency Bank Skew Part to Part Skew Pulse Skew (Fig. 1) (Fig. 2) (Fig. 3) RL = 100 , CL = 5 pF, Fig. 5, 6) (Fig. 5, 6) 700 Typ. 220 2 900 50 100 50 Max. 300 2.5 ps ns MHz ps Unit
NOTE 4: Generator waveforms for all test conditions: f=1MHz, ZO = 50 (unless otherwise specified).
CONTROL REGISTER TIMING CHARACTERISTICS (TA = -40 to 85 C, VCC = 2.5V 5%, EN=H, unless otherwise specified (Figure 4)
Value Symbol fMAX ts th trem tW Parameter Maximum Frequency of Shift Register Clock to SI Setup Time Clock to SI Hold Time Enable to Clock Removal Time Minimum Clock Pulse Width (Fig. 7) (Fig. 7) (Fig. 7) (Fig. 7) (Fig. 7) 3 Test Conditions Min. 100 Typ. 150 2 1.5 1.5 Max. MHz ns ns ns ns Unit
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STLVD111
SPECIFICATION OF CONTROL REGISTER The STLVD111 is provided with a 11 bit shift register with a Serial In and a Control Register. The purpose is to enable or power of each output clock channel and to select the clock input. The STLVD111 provides two working modality: PROGRAMMED MODE (EN=1) The shift register have a serial input to load the working configuration. Once the configuration is loaded with 11 clock pulse, another clock pulse load the configuration into the control register. The first bit on the serial input line enables the outputs Q9 and Q9, the second bit enables the outputs Q8 and Q8 and so on. The last bit is the clock selection bit. To restart the configuration of the shift register a reset of the state machine must be done with a clock pulse on CK and the EN set to Low. The control register shift register can be configured on time after each reset. STANDARD MODE (EN=0) In Standard Mode the STLVD111 isn't programmable, all the clock outputs are enabled. The LVDS clock input is selected from Clock 0 or Clock 1 with the SI pin as shown in the Truth Table below. TRUTH TABLE OF STATE MACHINE INPUTS
EN L L H H L SI L H L H X CK X X OUTPUT All Output Enabled, Clock 0 selected, Control Register disabled All Output Enabled, Clock 1 selected, Control Register disabled First stage stores "L", other stages store the data of previous stage First stage stores "H", other stages store the data of previous stage Reset of the state machine, Shift register and Control Register
SERIAL INPUT SEQUENCE
BIT#10 CLK_SEL BIT#9 Q0 BIT#8 Q1 BIT#7 Q2 BIT#6 Q3 BIT#5 Q4 BIT#4 Q5 BIT#3 Q6 BIT#2 Q7 BIT#1 Q8 BIT#0 Q9
TRUTH TABLE OF THE CONTROL REGISTER
BIT#10 L H X BIT#(0-9) H H L Qn(0-9) Clock 0 Clock 1 Qn Output Disabled
TRUTH TABLE
CK L L L L L L EN L L L L L L All drivers enable SI L L L H H H CLK 0 L H Open X X X CLK 0 H L Open X X X CLK 1 X X X L H Open CLK 1 X X X H L Open Q (0-9) L H L L H L Q(0-9) H L H H L H
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STLVD111
LOGIC DIAGRAM
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STLVD111
Figure 1 : BANK SKEW - tsk(b)
Figure 2 : PART TO PART SKEW - tsk(PP)
Figure 3 : PULSE SKEW - tsk(P)
tsk(b): BANKSKEW is the magnitude of the time difference between outputs with a single driving input terminal tsk(pp): PART TO PART SKEW is the magnitude of the difference in propagation delay times between any specific terminals of two devices when both devices operate with the same input signals, the same supply voltages, and the same temperature, and have identical packages and test circuits. tsk(b): PULSE SKEW is the magnitude of the time difference between the high to low and low to high propagation delay times at an output.
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STLVD111
Figure 4 : VOLTAGE AND CURRENT DEFINITION
Figure 5 : TEST CIRCUIT AND VOLTAGE DEFINITION FOR THE DIFFERENTIAL OUTPUT SIGNAL
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STLVD111
Figure 6 : DIFFERENTIAL RECEIVER TO DRIVE PROPAGATION DELAY AND DRIVE TRANSITION TIME WAVEFORMS
Figure 7 : SET-UP, HOLD AND THE REMOVAL TIME, MAXIMUM FREQUENCY, MINIMUM PULSE WIDTH WAVEFORMS
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STLVD111
TQFP32 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 B C D D1 D3 E E E1 E3 L L1 K 0 0.45 0.05 1.35 0.30 0.09 9.00 7.00 5.60 0.80 9.00 7.00 5.60 0.60 1.00 3.5 7 0 0.75 0.018 1.40 0.37 TYP MAX. 1.6 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.0035 0.354 0.276 0.220 0.031 0.354 0.276 0.220 0.024 0.039 3.5 7 0.030 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.0079 inch
D D1 D3 A1
17 16
0.10mm .004 Seating Plane
A A2
24 25
E3
E1
B
E
32 1 8
9
B C L K
e L1
TQFP32
0060661/C
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STLVD111
Tape & Reel TQFP32 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 9.5 9.5 2.1 3.9 11.9 12.8 20.2 60 22.4 9.7 9.7 2.3 4.1 12.1 0.374 0.374 0.083 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.382 0.382 0.091 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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STLVD111
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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